The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for device pitch reduction for integrated circuits. Merely by way of example, the invention has been applied to integrated circuits including array and periphery regions. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to forming patterns having width and spacing smaller than the minimum feature size.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a tenth of a micron across.
Making devices smaller is very challenging, as each process and equipment used in IC fabrication has a limit. Conventional processes usually are limited by a minimum features size that can be manufactured reproducibly. For example, device pitch of an integrated circuit, which is often used to measure the dimension of repeated lines and spaces, is often limited by the lithographic equipment and processes. As the half-pitch becomes less than 65 nm, especially less than 45 nm, lithographic processes often become difficult.
Accordingly, there is a need for improved pattern forming techniques that are not limited by the minimum feature size of conventional processing equipment and processes.